At-speed scan testing is an efficient test method for testing the internal functionality of integrated circuits, so called circuits under tests (CUT). For example, the maximum operation frequency of the CUT or at least parts of the CUT may be determined by pre-loading functional blocks of a scan chain with predefined set values and placing the scan chain into a functional mode thereby launching the function of the functional blocks. In a capture phase following the launch the output values of the functional blocks may be captured sequentially and analysed for coherence with an expected test outcome depending on the input set value pattern.
The essence of such at-speed scan testing lies in initializing the functional elements of a scan chain such as flip-flops with predefined values of a test pattern, usually by “shifting” the data items into the flip-flops via external access ports or scan-in pins using a test shift clock which may be slower than the usual functional clock of the CUT. Upon shifting the critical paths under test are launched and the states of the flip-flops are sampling in a capture operation. The capture operation may be applied in the faster functional clock regime, resulting in a so called AC scan. If the CUT is fully operational the transition will timely propagate to the end of the scan chain resulting in the correct, i.e. expected capture value pattern. In case of unwanted delays causing a slow propagation, the transition from launch to capture will result in an erroneous, i.e. unexpected capture value pattern so that defects in the CUT may be detected.
FIG. 1 exemplarily shows the sequence of shift cycles S, launch cycle L and capture cycle C for a single scan chain of a CUT in the upper diagram DC for the text clock signal CLK. During the shift cycles S a slow clock frequency is applied, while during the launch cycle L and the capture cycle C the full functional fast clock frequency is applied. The diagram DP below exemplarily indicates the typical distribution of power consumption P in the CUT which is induced by the increased switching activity during the shift cycles S. Any of the flip-flops of the scan chain may potentially toggle, and the transitions due to the toggling flip-flops propagate into the scan chain under test, potentially triggering additional transitions there. As a result—and as shown schematically in the power distribution diagram D2—at-speed scan tests may suffer from high peak power during certain critical phases in the scanning procedure stemming from large supply currents that causes large voltage drops over the CUT.
The type of at-speed scan test depicted in FIG. 1 is a so called “Launch-off-shift” (LOS) scan test which provides a better coverage of the CUT while at the same time involves shorter testing durations.
Several approaches have been pursued in the prior art to combat the high power peaks during at-speed scan testing which may create supply voltage noise potentially altering the operating frequency of the CUT thereby causing timing problems such as hold-time violations. Especially hold-time variations may severely impact the testing function and lead to incorrect conclusions drawn from evaluating the captured test patterns.
Bosio, A. et al.: “Power-Aware Test Pattern Generation for At-Speed LOS Testing”, 2011 Asian Test Symposium, November 2011, pages 506-510, disclose a smart X-filling framework for launch-off-capture (LOC) at-speed scan tests which are able to adapt peak power consumption during the launch-to-capture cycle according to the functional power, i.e. the power consumption of the circuit in functional mode.
Mentor Graphics Corporation: “Tessent TestKompress User's Guide”, 2011, page 134, discloses a method to control shift power by changing the shift data through a combination of hardware and software for the shift cycles in at-speed scan tests.
Lin, X. et al.: “Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells”, Journal of Electronic Testing, Volume 24, Number 4, pages 327-334 disclose a signal probability based approach for launch-off-capture at-speed scan tests to identify a set of power sensitive scan cells the output of which is frozen using additional hardware during scan shifting in order to reduce the shift power consumption.
The document U.S. Pat. No. 8,205,125 B2 discloses a test controller for at-speed scan testing an integrated circuit which implements an enhanced method for launch-off-shift testing with reduced delay and optimized synchronicity for different scan chains.
The document U.S. Pat. No. 7,987,401 B2 discloses a method for generating self-synchronized launch-off-shift capture pulses using on-chip phase locked loops for at-speed scan testing in order to achieve better coverage of multiple frequency operated clock domains.
Badereddine, N. et al.: “Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics”, Design and Test of Integrated Systems in Nanoscale Technology, 2006, DTIS 2006, International Conference on, September 2006, pages 359-364, disclose reducing high current levels during an at-speed scan test cycle based on power-aware assignment of “don't care” bits in deterministic test patterns.
The document U.S. 2008/0222741 A1 discloses a chip including circuitry to provide differently skewed test clock signals to the registers of different scan chain segments, respectively, in order to spread the power consumption of the different scan chain segments during the scan input periods of an at-speed scan test.
The document U.S. 2007/0162805 A1 discloses cycling the shift phases of different scan chain domains of an integrated circuit under scan-at-speed testing in an altering fashion, so that the power consumption of the integrated circuit during the shift phases is spread out.
There is a need for solutions which reduce the power consumption in the LOS cycle of an LOS at-speed scan testing architecture of a CUT.